1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of transistors having strained channel regions by using stress-inducing sources to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
Generally, a plurality of process technologies are currently practiced to fabricate integrated circuits, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode located close to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region is a dominant factor that determines the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is an important design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith, such as reduced controllability of the channel, also referred to as short channel effects, and the like, that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For instance, the thickness of the gate insulation layer, typically an oxide-based dielectric, has to be reduced when reducing the gate length, wherein a reduced thickness may result in increased leakage currents, thereby posing limitations for oxide-based gate insulation layers at approximately 1-2 nm. Thus, the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques, for example, for compensating for short channel effects with oxide-based gate dielectric scaling being pushed to the limits with respect to tolerable leakage currents. It has, therefore, been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the problems encountered with the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance, by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating uniaxial tensile strain in the channel region along the channel length direction for a standard crystallographic orientation increases the mobility of electrons, which, in turn, may directly translate into a corresponding increase in the conductivity. On the other hand, uniaxial compressive strain in the channel region for the same configuration may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
In some approaches, external stress created by, for instance, permanent overlaying layers, spacer elements and the like is used in an attempt to create a desired strain within the channel region. Although a promising approach, the process of creating the strain in the channel region by applying a specified external stress may depend on the efficiency of the stress transfer mechanism for the external stress provided, for instance, by contact layers, spacers and the like into the channel region to create the desired strain therein. Thus, for different transistor types, differently stressed overlayers have to be provided, which may result in a plurality of additional process steps, wherein, in particular, any additional lithography steps may significantly contribute to the overall production costs. Moreover, the amount of stress-inducing material, and in particular the intrinsic stress thereof, may not be arbitrarily increased without requiring significant design alterations. For example, the degree of tensile stress in corresponding portions of the dielectric layer formed above an N-channel transistor may require development of new deposition recipes, while significantly higher compressive stress may be provided by presently established techniques, thereby creating an imbalance with respect to performance of NMOS and PMOS transistors.
In still a further approach, a substantially amorphized region may be formed adjacent to the gate electrode at an intermediate manufacturing stage, which may then be re-crystallized in the presence of a rigid layer formed above the transistor area. During the anneal process for re-crystallizing the lattice, the growth of the crystal will occur under stress conditions created by the overlayer and result in a strained crystal. After the re-crystallization, the stress-inducing layer may be partly or completely removed, wherein, nevertheless, a certain amount of strain may be “conserved” in the re-grown lattice portion. This effect is generally known as stress memorization. Although the exact mechanism is not yet fully understood, it is believed that, upon re-crystallization of the substantially amorphized material, the increased volume of the amorphous material compared to the crystalline material may be substantially maintained due to the presence of the rigid surface layer that reduces or prevents the natural volume reduction which would usually occur during the re-crystallization. Hence, the strained re-grown crystalline material may induce a corresponding tensile strain in the region adjacent to the re-crystallized region of increased volume. The tensile strain may thus also be maintained after removal of a portion or all of the rigid surface layer.
Since many efficient strain-inducing mechanisms are available for PMOS transistors, such as embedded strained silicon/germanium material, stressed contact etch stop layers of very high intrinsic compressive stress and the like, respective strain engineering techniques may be desirable to preferably enhance performance of NMOS transistors.
However, currently practiced stress memorization techniques, although providing moderate advantages in device performance, may not provide the potential for significantly extending the limitations of performance gain of NMOS transistors while not unduly contributing to process complexity of the overall manufacturing process. Moreover, the applying stress memorization techniques to PMOS and NMOS transistors may result in a degradation of performance of PMOS transistors, which may partially offset the performance gain of the NMOS transistors. For this reason, selective stress memorization approaches may be considered, in which the rigid material layer may be removed from the PMOS transistors prior to actually re-crystallizing the drain and source areas of the PMOS and NMOS transistors, thereby, however, contributing to overall process time and complexity. In addition, the required mask and selective etch steps may contribute to an increased probability of reducing production yield, although well-established recipes may be used, while experimental data seem to indicate that PMOS degradation may not be fully addressed by these selective stress memorization techniques.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.